The improved photovoltaic devices disclosed herein (1) exhibit increased operational reliability, (2) exhibit increased operational efficiency, and (3) are fabricated in a manner which results in increased yields. Also disclosed are methods for the fabrication of said improved photovoltaic devices. The present invention has particular applicability to (1) large area, thin film, amorphous photovoltaic devices wherein the active semiconductor elements thereof are deposited onto a substrate electrode as relatively thin layers which are subsequently covered by a second electrode, and (2) the fabrication of such thin film, large area photovoltaic devices from amorphous semiconductor alloys.
Single crystal photovoltaic devices, especially crystalline silicon photovoltaic devices have been utilized for some time as sources of electrical power because they are inherently non-polluting, silent and consume no expendable natural resources in their operation. However, the utility of such devices is limited by problems associated with the manufacture thereof. More particularly, single crystal materials (1) are difficult to produce in sizes substantially larger than several inches in diameter, (2) are thicker and heavier than their amorphous counterparts; and (3) are expensive and time consuming to fabricate.
Recently, considerable efforts have been made to develop systems for depositing amorphous semiconductor materials, each of which can encompass relatively large areas, and which can be doped to form p-type and n-type materials for the production of p-i-n type photovoltaic devices which are, in operation, substantially equivalent to their crystalline counterparts. It is to be noted that the term "amorphous", as used herein, includes all materials or alloys which have long range disorder, although they may have short or intermediate range order or even contain, at times, crystalline inclusions.
It is now possible to prepare amorphous silicon alloys by glow discharge deposition or vacuum deposition techniques, said alloys possessing (1) acceptable concentrations of localized states in the energy gaps thereof, and (2) high quality electronic properties. Such techniques are fully described in U.S. Pat. No. 4,226,898, entitled Amorphous Semiconductors Equivalent To Crystalline Semiconductors, issued to Stanford R. Ovshinsky and Arun Madan on Oct. 7, 1980; U.S. Pat. No. 4,217,374, of Stanford R. Ovshinsky and Masatsugu Izu, which issued on Aug. 12, 1980, also entitled Amorphous Semiconductors Equivalent To Crystalline Semiconductors; and U.S. Pat. No. 4,517,223 of Stanford R. Ovshinsky, David D. Allred, Lee Walter, and Stephen J. Hudgens entitled Method Of Making Amorphous Semiconductor Alloys And Devices Using Microwave Energy. As disclosed in these patents, fluorine introduced into the amorphous silicon semiconductor layers operates to substantially reduce the density of the localized states therein and facilitates the addition of other alloying materials, such as germanium.
The concept of utilizing multiple cells, to enhance photovoltaic device efficiency, was described at least as early as 1955 by E. D. Jackson in U.S. Pat. No. 2,949,498 issued Aug. 16, 1960. The multiple cell structures therein discussed utilized p-n junction crystalline semiconductor devices. Essentially the concept employed different band gap devices to more efficiently collect various portions of the solar spectrum and to increase open circuit voltage (Voc). The tandem cell device (by definition) has two or more cells with the light directed serially through each cell. In the first cell a large band gap material absorbs only the short wavelength light, while in subsequent cells smaller band gap materials absorb the longer wavelengths of light which pass through the first cell. By substantially matching the generated currents from each cell, the overall open circuit voltage is the sum of the open circuit voltage of each cell, while the short circuit current thereof remains substantially constant. The multiple cells preferably include a back reflector for increasing the percentage of incident light reflected from the substrate back through the semiconductor layers of the cells. It should be obvious that the use of a back reflector increases the operational efficiency of the multiple cells. Accordingly, it is important that any layer deposited atop the substrate be transparent to pass a high percentage of incident light from the reflective surface of the back reflector through the semiconductor layers.
Unlike crystalline silicon which is limited to batch processing for the manufacture of solar cells, amorphous silicon alloys can be deposited in multiple layers over large area substrates to form solar cells in a high volume, continuous processing system. Such continuous processing systems are disclosed in the following U.S. Patents: No. 4,400,409 entitled for A Method Of Making P-Doped Silicon Films And Devices Made Therefrom; No. 4,542,711 entitled for Continuous Systems For Depositing Amorphous Semiconductor Material; No. 4,410,558, entitled for Continuous Amorphous Solar Cell Production System; No. 4,438,723 entitled for Multiple Chamber Deposition And Isolation System And Method; No. 4,492,181 entitled for Method And Apparatus For Continuously Producing Tandem Amorphous Photovoltaic Cells; and No. 4,485,125 entitled for Method and Apparatus For Continuously Producing Tandem Amorphous Photovoltaic Cells. As disclosed in these applications, a substrate may be continuously advanced through a succession of deposition chambers, wherein each chamber is dedicated to the deposition of a specific semiconductor material. In making a photovoltaic device of p-i-n type configurations, the first chamber is dedicated for depositing a p-type semiconductor alloy, the second chamber is dedicated for depositing an intrinsic amorphous semiconductor alloy, and the third chamber is dedicated for depositing an n-type semiconductor alloy. Since each deposited semiconductor alloy, and especially the intrinsic semiconductor alloy, must be of high purity; (1) the deposition environment in the intrinsic deposition chamber is isolated, by specially designed gas gates, from the doping constituents within the other chambers to prevent the diffusion of doping constituents into the intrinsic chamber; (2) the substrate is carefully cleansed prior to initiation of the deposition process to remove contaminants; (3) all of the chambers which combine to form the deposition apparatus are sealed and leak checked to prevent the influx of environmental contaminants; (4) the deposition apparatus is pumped down and flushed with a sweep gas to remove contaminants from the interior walls thereof; and (5) only the purest reaction gases are employed to form the deposited semiconductor materials. In other words, every possible precaution is taken to insure that the sanctity of the vacuum envelope formed by the various chambers of the deposition apparatus remains uncontaminated by impurities, regardless of origin.
The layers of semiconductor material thus deposited in the vacuum envelope of the deposition apparatus may be utilized to form a photovoltaic device including one or more p-i-n cells, one or more n-i-p cells, a Schottky barrier, photodiodes, phototransistors, or the like. Additionally, by making multiple passes through the succession of deposition chambers, or by providing an additional array of deposition chambers, multiple stacked cells of various configurations may be obtained.
As is obvious from the foregoing, thin film amorphous semiconductor materials offer several distinct advantages over crystalline materials, insofar as they can be easily and economically fabricated by the newly developed mass production processes. However, in the fabrication of semiconductor material by the aforementioned processes, the presence of current-shunting defects has been noted. These defects have (1) seriously impaired the performance of the photovoltaic devices fabricated therefrom and (2) detrimentally affected production yield. These process-related defects are thought to either (1) be present in the morphology of the substrate electrode, or (2) develop during the deposition of the semiconductor layers. It is to the end of eliminating, or at least substantially reducing the effects of these current-shunting defects to which the instant invention is directed.
The most important of said defects may be characterized as "shunt", or "short-circuit" defects or defect regions. Before the suspected causes of these defects are explained, it is helpful to note the thicknesses of the deposited semiconductor layers. A typical p layer may be only on the order of 400 angstroms thick, a typical i layer may be only be on the order of 3500 angstroms thick, and a typical n layer may be only on the order of 200 angstroms thick, thereby providing a total semiconductor body thickness of only about 4100 angstroms. It should therefore be appreciated that irregularities, however small, are not easy to cover by the deposited semiconductor layers.
Shunt defects are present when one or more low resistance current paths develop between the electrodes of the photovoltaic device. Under operating conditions, a photovoltaic device in which a shunt defect has developed, exhibits either (1) a low power output, since electrical current collected at the electrodes thereof flows through the defect region (the path of least resistance) in preference to an external load, or (2) complete failure where sufficient current in shunted through the defect region to "burn out" the device.
While shunt-type defects always deleteriously effect the performance of photovoltaic devices, their effect is greatest when the devices in which they are incorporated are operated under relatively low illumination, such as room light, vis-a-vis, high intensity illumination such as AM 1. This occurs because, in a photovoltaic device, photo-generated current increases linearly with increasing illumination, while the resulting voltage increases exponentially with increasing illumination. In other words, voltage attains a relatively high value under low illumination, the value increasing only slightly as the intensity of the illumination is increased. The result is that under low illumination a relatively high voltage potential is present, said potential adapted to preferentially drive the relatively small number of current carriers through the path of least resistance, i.e., the low resistance defect regions. In contrast thereto, under high illumination, a large number of current carriers are present and are driven by a potential of about the same magnitude as the potential which exists under low illumination. This larger number of current carriers compete for the paths of least resistance (through the defect regions). The result is that a proportionally smaller number of current carriers are able to pass through the limited number of available low resistance paths, thereby forcing the remainder of the current carriers to pass through the semiconductor material. Therefore, the loss of power resulting from the current-shunting effects of the defect regions will not be proportionally as great under high illumination as under low illumination.
Defects or defect regions, the terms being interchangeably used herein, are not limited to "overt" or "patent" short circuit current paths. In some cases the adverse effects of a defect are latent and do not immediately manifest themselves. Latent defects can give rise to what will be referred to hereinafter as an "operational mode failure", wherein a photovoltaic device, initially exhibiting satisfactory electrical performance, suddenly fails. The failures will be referred to in this application as operational mode failures regardless of whether the device was previously connected to a load for the generation of power, it only being necessary that the device was, at some time, subjected to illumination, thereby initiating the generation of carriers. This type of failure will be discussed in further detail hereinbelow. It is believed the shunt defects, both latent and patent, arise from one or more irregularities in the (1) morphology of the substrate material, or (2) in the growth of the semiconductor layers.
The first, and perhaps most important, source of the defects, i.e., the aforementioned morphological irregularities in the deposition surface of the substrate material will now be discussed. Even though the highest quality stainless steel is employed to serve as the substrate or base electrode upon which the semiconductor layers are successively deposited, it has been calculated that from 10,000 to 100,000 irregularities per square centimeter are present on the deposition surface thereof. Such irregularities take the form of projections, craters, or other deviations from a smooth finish and may be under a micron in (1) depth below the surface, (2) height above the surface, or (3) diameter. Regardless of their configuration or size, the defect may establish a low resistance current path through the semiconductor body, thereby effectively short-circuiting the two electrodes. This may occur in numerous ways. For instance, a spike projecting from the surface of the substrate electrode may be of too great a height to be covered by the subsequent deposition of semiconductor layers, and therefore, be in direct electrical contact with the other electrode when that electrode is deposited atop the semiconductor layers. Likewise, a crater formed in the surface of the substrate electrode may be of too small a size to be filled by the subsequent deposition of semiconductor layers and therefore, be in sufficient proximity to the other electrode, when that electrode is deposited atop the semiconductor layers, for electrical current to either (1) bridge the gap which exists between the electrodes, or (2) through actual use (the photo-induced generation of electrical current) of the photovoltaic device, cause the material of one of the electrodes to migrate toward and contact the other of the electrodes, and thereby pass electrical current therebetween. It is also possible that the semiconductor layers deposited onto the substrate are of poor quality, thereby providing a low resistance path for the flow of electrical current between the electrodes of the photovoltaic device.
Further, despite all the previously described efforts to maintain the vacuum envelope free of external contaminants; dust or other particulate matter, which somehow either (1) violates the sanctity of the vacuum envelope during the deposition of the semiconductor material, or (2) forms as a by-product of the deposition process is deposited atop the substrate electrode along with the semiconductor material. The contaminants interfere with the uniform deposition of the semiconductor layers and may establish the low resistance current path through which electrical current either (1) directly communicates, or (2) may, through operation of the device, develop communication with the two electrodes. Additionally, it is suspected that in some cases, the semiconductor material may form micro-craters or micro-projections during the deposition thereof, even absent the presence of contaminants or pollutants from external sources. Again, such morphological deviation from a perfectly smooth and even surface means that the substrate is covered by semiconductor material either (1) in an "ultra thin layer" (consider again that the total thickness of all semiconductor layers is only on the order of 4100 angstroms and any reduction in coverage is indeed an ultra thin layer) or (2) not at all. Obviously, when the upper electrode material is deposited across the entire surface of the semiconductor body, the defect regions cause the low resistance current path to develop, and electrical current is shunted therethrough. In still other cases involving defect regions, the presence of such defect regions are only detectable due to their deleterious effect upon the electrical and photoelectric properties of the resultant photovoltaic device. Finally, note the defects described hereinabove may not be sufficiently severe to divert all electrical current through the low resistance path. However, the diversion or shunting of any current therethrough represents a loss in operational efficiency of the photovoltaic device and should therefor be eliminated. Moreover, the shunting of even small amounts of current through each of thousands of defect regions may combine to cause major losses in efficiency. Based upon the foregoing, it should be apparent that a reduction in current flow through these defects and defect regions is critical to the fabrication of high-yield, high efficiency thin film photovoltaic devices.
Several approaches dealing with gross amplifications of this problem have been implemented by the Inventors and their colleagues. As described in U.S. Pat. No. 4,451,970 of Masatsugu Izu and Vincent Cannella, entitled System And Method For Eliminating Short Circuit Current Paths In Photovoltaic Devices, said application assigned to the assignee of the instant application, the shunting of current through defect regions is treated by substantially eliminating the defect regions as an operative area of the semiconductor device. This is accomplished in an electrolytic process where electrode material is removed from the periphery of the defect site, effectively isolating the defect region and preventing the flow of electrical current through the defect region. However, the process described in the '970 patent is current dependent, i.e., the greater the current flowing through a particular area of the device, such as a defect region, the greater the amount of electrode material (in the preferred embodiment indium tin oxide) is removed. Consequently, said short circuit eliminating process performs admirably in removing the electrode material from the periphery of a large defect, and thereby preventing all current flow therethrough. However, it is not as successful in eliminating the flow of current between the electrodes in the thousands of defect regions which are relatively small. And, as previously mentioned, since a great many of relatively small current shunting paths, taken in toto, divert a substantial amount of current from its desired path of travel through the semiconductor layers, the flow of current through the low resistance current paths created by such small defect regions must also be eliminated or at least substantially reduced. Further, the electrolytic process described in the '890 application neither detects nor helps in preventing the formation of current-shunting paths in the case of operational mode failures.
In U.S. Pat. No. 4,419,530 of Prem Nath, entitled Improved Solar Cell and Method For Producing Same, and assigned to the assignee of the instant invention, there is described a method for electrically isolating small area segments of an amorphous, thin film, large area photovoltaic device. This is accomplished by (1) dividing the large area device into a plurality of small area segments, (2) testing the small area segments for electrical operability, and (3) electrically connecting only those small area segments exhibiting a predetermined level of electrical operability, whereby a large area photovoltaic device comprising only electrically operative small area segments is formed. One cause of the electrical inoperability (failure of the device to meet predetermined minimum specifications) of small area segments is the presence of defect regions which operate to shunt current through low resistance paths. The method of solving the problem of defect regions in U.S. Pat. No. 4,419,530 while effective, eliminates rather large sections of the photovoltaic device. The output of the device is significantly reduced as compared to the output which could be realized if only the precise defect region was eliminated.
Further, both of the foregoing methods relate to "after market" techniques which are applicable to (1) isolate only gross defect-containing regions of a photovoltaic device, and (2) prevent any and all current flow through those defect-containing regions. Accordingly, a need still exists for a non-destructive method of substantially eliminating the deleterious effect of shunt defects, both large and small, whatever their origin, (1) prior to the completion of the photovoltaic device, i.e., prior to the deposition of the top electrode, (2) without operatively removing large portions of the active semiconductor body, and (3) while maintaining an acceptable level of current flow across the entire surface of the device.
Process related, short-circuiting defect problems arising in the fabrication of thin film photovoltaic devices were recognized as early as 1978 by scientists at R.C.A., who then attempted several methods for the cure of same. U.S. Pat. No. 4,162,505 of Joseph L. Hanak, assigned to R.C.A., entitled Inverted Amorphous Silicon Solar Cell Utilizing Cermet Layers, discloses the use of a thick film (2000 to 15000 angstroms) cermet layer to provide a ballast resistance which affords some protection from the effects of shorts and shunts in an inverted n-i-p, amorphous silicon solar cell. The thick cermet layer is disposed on the side of the amorphous silicon body opposite that side upon which light is incident. The location of the cermet layer (the side opposite incident light) in the R.C.A. cell is mandated by the thickness and consequent opacity thereof. If it were placed atop the incident side of the silicon body, the cermet layer would absorb most of the incident light, thereby rendering the cell inoperative. In the '505 patent, an additional thin (50-200 angstrom), high work function cermet layer is disposed atop the illuminated surface of the silicon body, the function of said thin layer being to provide ohmic contact between the electrode material and the p+ silicon layer. The patent neither discloses nor suggests that a short amelioration function may be attributable to the thin cermet layer.
Although U.S. Pat. No. 4,166,918 of Gerald E. Nostrand, et al, also assigned to R.C.A. and entitled: Method of Removing The Effects Of Electrical Shorts And Shunts Created During The Fabrication Process Of A Solar Cell, discloses a method of removing shunts by operatively disposing a thick cermet layer on the bottom surface of the cell, said thick cermet layer does not, in and of itself, cure the adverse effects of shorts and shunts. Nostrand, et al, must subsequently apply a reverse-bias voltage of sufficient magnitude to burn out the current-shunting defects in cermet containing solar cells. Only in this manner are Nostrand, et al able to improve their current and voltage output. The patent does not suggest the use of a cermet layer, which, taken alone, is capable of removing short circuit flow paths.
U.S. Pat. No. 4,167,015 of Joseph J. Hanak, assigned to R.C.A. and entitled: Cermet Layer For Amorphous Silicon Solar Cells is limited to the use of a thin (50-200 angstroms), high work function cermet layer either: (1) to form a Schottky barrier with amorphous silicon, or (2) as an aid to formation of an ohmic junction between the p+ amorphous silicon layer and the electrode in a p-i-n device. No disclosure of the use of a cermet layer for reducing the effects of existing, or preventing the generation of additional, shorts or shunts is provided. As succinctly stated in Column 4, lines 4-10 of the '015 patent: "Although the transparent high work function metal cermet would appear not to be needed in a PIN solar cell structure, the cermet adheres well to the p+ amorphous silicon layer, permits the formation of a good ohmic contact to the transparent conducting oxide layer 32 . . . ".
A general theoretical discussion of the use of a thin film series resistor to reduce or eliminate the effects of shorts in large area thin film photovoltaic devices was presented by Joseph J. Hanak in a paper entitled Progress Toward Large Area Amorphous Silicon Solar Cells, published in the proceedings of the "Fourteenth IEEE Photovoltaic Specialists Conference 1980," p. 623. Dr. Hanak concludes therein that a layer of cermet material, of appropriate resistance, can limit the harmful effects of shorts and shunts. However, his discussion of (1) barrier layer materials is carefully restricted to thick film cermets similar to those disclosed in the aforementioned R.C.A. assigned patents, and (2) the cermet layer, in order to act as a short preventing barrier, must be applied in a thickness of 5000-10000 angstroms, a thickness range which would not provide a transparent layer. Also discussed in the Hanak paper is the reverse-bias short removal technique described hereinabove with reference to the '918 patent.
U.S. Pat. No. 4,251,286, of Allen M. Barnett, entitled Thin Film Photovoltaic Cells Having Blocking Layers, describes a blocking layer deposited in a photovoltaic cell which is adapted to avoid electrical path failures by preventing undesired electrical contact which might otherwise occur between (1) the transparent and opaque electrodes of the cell, or (2) one of the electrodes and the remote semiconductor layer. Barnett's cells are fabricated from cadmium sulfide or cadmium zinc sulfide with a heterojunction of copper sulfide. His preferred embodiment includes a blocking layer formed from zinc sulfide which is 1000 angstroms to 5 microns thick. It should be readily apparent, in view of the discussion which preceded this paragraph, that even a 1000 angstrom thick layer of zinc sulfide would not provide adequate transparency to permit the use of that material adjacent the transparent electrode without blocking the entrance into the semiconductor layers of a substantial percentage of incident light. In an alternate embodiment, Barnett proposes the application of discontinuous insulating materials either by oxidizing the entire exposed surface of the semiconductor material, or by depositing a very thin insulating layer atop the semiconductor material prior to deposition of the second electode.
Although Barnett does disclose the broad concept of employing a blocking layer to prevent short circuit paths, his teachings are not applicable to the production of a high quality photovoltaic device for the following reasons. First, Barnett's blocking layer is not formed of a material which is compatable with amorphous silicon alloys. If Barnett's blocking layer materials were employed in combination with the semiconductor layers utilized in the instant Inventor's cells, high losses in operational efficiencies of the cells would result. Second, Barnett's blocking layer is only adapted for operative disposition at the back side of a photovoltaic cell, vis-a-vis, a back reflective cell which requires that light strike the reflective back layer without absorptive losses due to the blocking layer. If a 1000 angstrom thick layer of zinc sulfide were employed at the incident side of the cell, too much light would be absorbed by the zinc sulfide layer. And even if the blocking layer were applied at the rear side of the cell, too much light would be absorbed to permit the efficient use of a back reflector. Third, Barnett suggests the use, albeit, in very sketchy forms, of a copper oxide blocking layer. While no specific thickness is disclosed, giving said copper oxide layer a thickness of 1000 angstroms (the thinnest range described for any blocking layer), Barnett is unable to provide an upper blocking layer which does not substantially interfere with the passage of incident light.
The instant invention, as will be described in greater detail hereinbelow, provides an improved photovoltaic device which (1) includes a transparent, easily fabricated barrier layer; and (2) provides relief from the effects of current-shunting defects, both patent and latent. Neither the materials from which the transparent barrier layer is fabricated, nor the techniques for fabricating the barrier layer are present in the prior art.
The configurations of short circuit preventing cermet materials disclosed in the R.C.A. patents are counterproductive if used in combination with the photovoltaic devices of the instant invention. More particularly, R.C.A.'s disclosures, taken singly or collectively, require the cermet materials to be deposited in thicknesses of 2000 to 15,000 angstroms in order to adequately limit the flow of current through defect sites. However, the opacity of a layer of cermet material of such thickness is too great for use in the photovoltaic devices.
Specifically, if a cermet layer of at least 2000 angstrom thickness were disposed upon the top surface of the semiconductor body of a p-i-n solar cell, photons from incident light would be unable to reach the active semiconductor body of the solar cell, thereby rendering the cell ineffective for its intended photovoltaic purpose. Furthermore, the photovoltaic cells of the instant invention incorporate a reflective substrate layer which redirects unused light energy which has made a first pass through the semiconductor body back through that body to increase device efficiency. The presence of an opaque, light-absorbing barrier layer atop the reflective substrate would prevent reflection of unused light, thereby preventing efficient use of incoming energy. While a substantially opaque barrier layer might be suitable for use in photovoltaic cells made according to the R.C.A. design, such an opaque layer, which is not necessary to provide ohmic contact between the p+ layer and the substrate, would detrimentally affect the performance of the Inventors' devices. Accordingly, the instant invention provides a substantially transparent barrier layer suitable for use on either or both surfaces of the semiconductor body and which is formed of materials neither disclosed nor suggested in the aforementioned R.C.A. prior art.
In addition to their opacity, R.C.A. cermet materials present process limitations which are not encountered when utilizing the materials disclosed in the practice of the instant invention. Firstly, the 2000-15000 angstrom thickness of the cermet layers (required by R.C.A.) necessitates a lengthy deposition procedure, which is undesirable in a high volume mass production process. Second and more importantly, the deposition of the cermet material is accomplished by a sputtering process, which is inherently destructive and therefore likely to introduce new defects in the material onto which it is deposited. More particularly, sputtering is an energetic coating process in which particles having high kinetic energy bombard the layer to be coated. These energetic particles are likely to harm either the entire 4100 angstrom thick amorphous silicon body of the cell or at least the top layer thereof onto which they are deposited. Such damage can result in immediate failure of the device, or can lead to operational mode failure. Although, the damage caused by the sputtering process may be controlled to some degree by decreasing the sputter rate, the deposition process is simultaneously slowed, thereby increasing the time required to deposit a layer of a given thickness.
In contrast thereto, the instant barrier layer is preferably deposited onto the semiconductor body by thermal evaporation, so as to obviate the problems of damage which result from sputtering techniques. Thermal evaporation processes (1) are reliable, (2) are rapid, (3) are easy to control, (4) utilize relatively simple equipment compared to sputter-coating processes, (5) have high deposition rates, and (6) do not damage the semiconductor body. Furthermore, the layers of material utilized in the instant invention are of approximately an order of magnitude lower thickness as compared to those thicknesses of the cermet materials described in the R.C.A. patents, thereby providing for (1) a more rapid fabrication procedure, and (2) transparency of those layers. Lastly, the problem of operational mode failure is neither recognized nor addressed by the prior art, and, therefore the method of preventing those failures cannot be anticipated by said prior art.
According to the principles of the preferred embodiment of the instant invention, a transparent "barrier layer" having a resistivity greater than the resistivity of the transparent electrode is interposed between one of the electrodes and the semiconductor body of the photovoltaic device. This barrier layer functions as a resistor to limit the flow of electrical current shunted through the short circuit defect path(s) of the photovoltaic devices. By selecting a barrier layer of optimized (1) resistivity, (2) thickness, and (3) transparency, the low resistance current path(s) may be substantially eliminated, while the negative effects of the barrier layer (including losses in efficiency and photoelectrical properties) on the photovoltaic device will be minimized. The method of depositing a barrier layer to substantially eliminate both patent and latent defect regions described herein, is readily adaptable for inclusion as one of the processing steps in the fabrication of amorphous, large area, thin film photovoltaic devices. The barrier layer may be deposited by techniques such as evaporation, vacuum deposition, chemical vapor deposition, or other processes which are compatible with the deposition steps utilized to fabricate the semiconductor layers and the electrode layers of the photovoltaic device. Accordingly, the instant invention provides an economical method for the high yield manufacture of improved amorphous, thin film, large area photovoltaic devices which are substantially free of low resistance current paths through which electrical current is likely to be shunted between electrodes, regardless of whether said low resistance paths are either initially or latently manifested.
These and other advantages of the instant invention will become apparent from the drawings, the detailed description of the invention and the claims which follow.